01 · Processor programme
SQPU256
The flagship superconducting quantum processor target and the integrated system architecture required to control, calibrate and operate it.
Advay Labs · Superconducting quantum hardware
Engineering SQPU256: a 256-qubit superconducting quantum processor platform.
A useful quantum computer is not a chip — it is a processor, a package, a cryogenic environment, a control system, a calibration method and a software stack that have to work as one. Advay Labs is engineering all of it around SQPU256, advancing through measured hardware milestones rather than announcements.
SQPU256Flagship processor programmeA 256-qubit superconducting quantum processor target, engineered as a complete system rather than an isolated chip.
Tile-1 → 16 → 64 → 256Evidence-gated progressionEach scale closes a defined set of device, package, control, calibration and manufacturing risks before the next begins.
Seven layersProcessor through runtimeDevice, fabrication, package, cryogenics, microwave control, calibration and software are developed as one coupled programme.
TvaritDigital engineering layerCircuit analysis, architecture mapping, resource projection and evidence-labelled reporting that feed measured data back into design.
The flagship programme
SQPU256 is the product. The complete system exists to make it work.
A useful quantum processor is not only a qubit chip. It is a tightly coupled system spanning device design, fabrication, packaging, cryogenics, microwave control, readout, calibration and workload mapping. Advay is developing these layers around one hardware programme and one evidence-gated route to scale.
02 · Hardware progression
Measured milestones
SQPU Tile-1, SQPU16 and SQPU64 are structured as learning stages toward SQPU256, with explicit technical questions and exit evidence.
03 · Research ecosystem
Defined collaboration interfaces
Advay engages laboratories, foundries, packaging and cryogenic teams, RF-control specialists, researchers and institutions through scoped technical workstreams.
SQPU256 at a glance
A hardware architecture designed for scalable learning.
The figures below describe scope, progression and method. Advay does not publish coherence, fidelity, gate-speed or yield numbers for a device that has not yet been fabricated and measured.
- Target scale: 256 superconducting qubits.
- Hardware progression: SQPU Tile-1 → SQPU16 → SQPU64 → SQPU256.
- System scope: processor, package, cryogenics, microwave control, readout, calibration and software interfaces.
- Engineering focus: frequency planning, coupler behaviour, readout organisation, crosstalk, yield, package parasitics and repeatable calibration.
- Development method: evidence-gated advancement from design and simulation to fabrication and measurement.
Why the programme is structured this way
Scale only after the hardware learning closes.
The programme separates ambition from evidence. Architecture and simulation guide decisions; fabrication and measurement determine what is physically true.
A processor is more than a qubit count
Scalable operation depends on device behaviour, package modes, control-channel density, calibration repeatability, readout organisation and software mapping working together.
Scale must follow measured learning
Moving directly to a larger architecture can multiply unresolved process, frequency, packaging and control risks. Advay uses intermediate hardware milestones to close them deliberately.
Claims must remain evidence-bound
Designed, simulated and projected results are useful, but they are not measured hardware performance. Every public statement must preserve that distinction.
Measured development programme
From first hardware learning to the SQPU256 target.
SQPU Tile-1, SQPU16 and SQPU64 are not separate products. They are controlled stages for closing the technical risks that determine whether the flagship architecture can scale credibly.
Architecture and partner closure
Define the design basis, public-safe interfaces, process assumptions, evidence gates and the route to fabrication and measurement.
SQPU Tile-1
A first measured hardware-learning milestone intended to compare engineering assumptions with physical device, package, cryogenic and control behaviour.
SQPU16
An intermediate scale intended to establish repeatable multi-qubit integration and calibration learning.
SQPU64
A system-scaling stage intended to stress integration, control density, readout organisation, calibration automation and operating stability.
SQPU256
The flagship target that consolidates measured design rules, manufacturing learning and integrated system methods from earlier stages.
Research and engineering partners
Collaborate where superconducting systems are hardest.
No group builds this stack alone. Advay works with partners who own a specific layer of the problem, on a scoped question with a defined output and a clear evidence boundary.
Foundries and process partners
Process review, test structures, design-for-manufacture feedback and controlled layout handoff, within an agreed confidentiality boundary.
Packaging and cryogenic facilities
Package concepts, shielding and thermalisation, interconnect design, cooldown access and measurement time on qualified cryogenic systems.
Microwave control and instrumentation
Signal generation and acquisition, amplification, filtering, channel scaling and the control-electronics interfaces an operable system depends on.
Measurement and calibration groups
Characterisation campaigns, automated calibration methods, drift and repeatability studies, and disciplined model reconciliation.
Universities and research groups
Joint research, student and doctoral projects, benchmark methodology, technical notes and co-authored publications with defined scope.
Institutional and national programmes
Long-horizon capability building where facilities, talent, research and hardware milestones need to be planned as one programme.
Enabling engineering layer
Tvarit supports the SQPU programme; it does not define the company.
Tvarit is Advay’s digital engineering environment for circuit analysis, architecture mapping, simulation, resource projection, noise sensitivity and evidence-labelled reporting. Outputs remain simulated or projected unless explicitly linked to measured hardware data.
- OpenQASM circuit analysis and ideal execution.
- Architecture mapping and resource projection.
- Noise, sensitivity and reference-profile analysis.
- Evidence-labelled reports and API workflows.
Research integrity
Every technical statement should show how it was established.
Advay distinguishes Designed, Simulated, Projected, Fabricated, Measured and Independently Reviewed work. Target performance is not presented as achieved performance, and simulation is not presented as physical measurement.
DesignedSimulatedProjectedFabricatedMeasuredIndependently reviewed
Institutional and strategic programmes
Some collaborations are larger than a single workstream.
Building superconducting quantum hardware requires facilities, fabrication access, cryogenic capacity, instrumentation, specialist people and sustained multi-year commitment. Where a partner wants to shape that programme rather than contribute to one part of it, Advay engages through a structured, confidential technical and programme review.
- A defined technical objective and the hardware milestone it maps to.
- The capability each side contributes — facilities, process access, instrumentation, people or programme resourcing.
- Evidence gates, review points and what constitutes completion for each stage.
- Confidentiality, publication rights and intellectual-property boundaries agreed before technical material is exchanged.
Frequently asked
Clear answers about the SQPU programme.
Advay Labs is developing SQPU256, a 256-qubit superconducting quantum processor target, together with the packaging, cryogenic, microwave-control, calibration and software interfaces required to operate it as an integrated system.
No. SQPU256 is a target architecture under development. Public communication must not imply that a 256-qubit Advay processor has been fabricated, measured or made commercially available unless that status is formally established.
They are progressive hardware-learning milestones toward SQPU256. Each stage is intended to close specific risks in device behaviour, integration, packaging, control, readout, calibration and manufacturing before increasing scale.
Tvarit is Advay’s digital engineering environment for OpenQASM circuit analysis, architecture mapping, simulation, resource projection, noise sensitivity and evidence-labelled reporting. It supports the SQPU programme but does not represent execution on an Advay physical QPU unless explicitly stated.
Public results are labelled as Designed, Simulated, Projected, Fabricated, Measured or Independently Reviewed. Each result should identify its method, assumptions, configuration, uncertainty and limitations.
Use the Contact page with a defined technical question, relevant capability, proposed contribution, expected output and practical next step. Advay prioritises focused workstreams with clear technical boundaries, and is actively looking for foundry, packaging, cryogenic, control, calibration and research partners.
Beyond single workstreams, Advay engages laboratories, universities, national programmes and strategic industrial partners around multi-year hardware milestones — where facilities, fabrication access, instrumentation, people and programme resourcing are planned together. These conversations run privately under an appropriate agreement through the institutional and strategic programme route on the Contact page.
Tvarit access covers software workflows: circuit analysis, architecture mapping, resource projection, noise sensitivity and evidence-labelled reporting. It does not purchase SQPU hardware, fabrication work, cryogenic measurement time, execution on an Advay physical QPU, or participation in the hardware development programme. Those are handled as separate technical engagements.
No. Public pages explain the system architecture, research areas and collaboration interfaces at a useful level, while proprietary dimensions, process parameters, layouts and partner-confidential information remain controlled.
Hardware collaboration
Help advance the next measured milestone.
Start a defined conversation around research, fabrication, packaging, cryogenics, RF control, calibration, institutional capability or a long-horizon programme partnership.
Start a technical conversation