Quantum processor
A coordinated superconducting device, coupling, readout and connectivity architecture developed under controlled design rules.
Flagship superconducting processor programme
SQPU256: Advay Labs’ 256-qubit superconducting quantum processor target.
SQPU256 is the flagship architecture under development at Advay Labs. The programme combines a superconducting quantum processing unit with the package, cryogenic, control, calibration and software interfaces required to operate it as a complete system.
Public status
Target architecture under development.This page does not claim that a 256-qubit Advay device has been fabricated, measured or made commercially available.Programme scope
What SQPU256 covers — and what is deliberately not stated here.
Scope, progression and method are public. Device performance is not: no coherence, fidelity, gate-speed, error-rate or yield figure appears on this site for a processor that has not yet been fabricated and measured.
- Target scale: 256 superconducting qubits.
- Hardware progression: SQPU Tile-1 → SQPU16 → SQPU64 → SQPU256.
- System scope: processor, package, cryogenics, microwave control, readout, calibration and software interfaces.
- Engineering focus: frequency planning, coupler behaviour, readout organisation, crosstalk, yield, package parasitics and repeatable calibration.
- Development method: evidence-gated advancement from design and simulation to fabrication and measurement.
System objective
A processor architecture designed around system constraints from day one.
SQPU256 is being developed with device behaviour, manufacturability, package integration, control density, readout organisation, calibration effort and workload mapping considered together. This reduces the risk of optimising one layer while making the complete system harder to operate.
The QPU is one component of the quantum computer.
The programme treats the processor die, package, cryogenic environment, electronics, calibration and software interfaces as mutually dependent engineering domains.
- Modular progression through smaller measured hardware stages.
- Yield-aware and control-aware architecture decisions.
- Explicit separation of design targets and achieved measurements.
- Public-safe collaboration interfaces with controlled proprietary detail.
Integrated system
Six public-facing engineering layers around one processor programme.
The descriptions below establish the technical scope without disclosing proprietary dimensions, process parameters, layouts or partner-confidential implementation details.
Fabrication pathway
Foundry collaboration, test structures, process assumptions and reviewable layout handoff without publishing proprietary geometry.
Package and cryogenic environment
Mechanical, electromagnetic, thermal and interconnect decisions treated as part of processor performance.
Microwave control and readout
The signal-generation, routing, conditioning and acquisition interfaces required to operate and observe the device.
Characterisation and calibration
A repeatable path from raw fabricated behaviour to an operable and modelled system.
Compiler and runtime interfaces
Circuit mapping and execution assumptions aligned to declared topology, gate, timing and control constraints.
Engineering principles
Modular. Yield-aware. Control-aware. Evidence-gated.
- Progress from test structures and Tile-1 to SQPU16, SQPU64 and the SQPU256 target.
- Treat fabrication variation, frequency allocation, package interactions and control constraints as first-order design inputs.
- Use simulation and imported engineering data to guide decisions, then reconcile models against physical measurements.
- Advance scale only when acceptance evidence and remaining risks are explicitly reviewed.
- Keep target performance, simulated results and measured outcomes clearly separated.
Collaboration interfaces
Where research and engineering partners can contribute.
Advay structures collaboration around a defined technical question, contribution, evidence output and next decision.
Device and fabrication
Process review, test structures, device learning, layout handoff and manufacturing feedback within controlled confidentiality boundaries.
Package, cryogenics and control
Package integration, electromagnetic and thermal review, cryogenic access, microwave control, readout and instrumentation.
Measurement, calibration and software
Characterisation campaigns, calibration workflows, benchmark methods, model reconciliation and compiler–hardware research.