Gate 1 · Partner path
Signed or written lab, foundry, packaging and cryogenic validation path.
Physical milestone
SQPU Tile-1 is the first investable hardware proof point.
SQPU256 remains the architecture target. Tile-1 is the evidence-gated physical MVP designed to prove the superconducting hardware learning loop.
Why Tile-1 first
Do not hide unknowns inside a 256-qubit first chip.
A small measured tile isolates the actual bottlenecks: junction variation, resonator collisions, packaging parasitics, cryogenic behaviour, RF-control constraints and calibration repeatability.
- 1–2 or 4–8 superconducting qubit test tile depending on partner capability
- Measured resonator and qubit frequencies with deviation from prediction
- T1, T2, readout and calibration measurements where supported by the test setup
- Packaging, cryogenic and RF-control observations captured as evidence
- Digital-twin model update after measured data is received
- Second-run design rules derived from the measured delta
Evidence gates
The first chip is judged by measured learning, not marketing scale.
Gate 2 · Design freeze
Tile design, frequency plan, readout approach, mask data and acceptance criteria locked.
Gate 3 · Fabrication return
Device returned with process metadata, inspection notes and packaging record.
Gate 4 · Cooldown and measurement
Measured device data captured with run logs, bounds and failure notes.
Gate 5 · Model update
Digital twin updated from measured delta and next design rules generated.
Tile-1 converts Advay from software narrative to hardware-learning company.
The milestone is designed for serious lab, grant, partner and investor diligence.
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